RC32434 processor equivalent, idt interprise integrated communications processor.
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32-bit CPU Core
– MIPS32 instruction set
– Cache Sizes: 8KB instruction and data caches, 4-Way set associative, cache line locking,.
that require integer arithmetic. The CPU core includes 8 KB instruction and 8 KB data caches. Both caches are 4-way set .
for MADDR[3:0] www.DataSheet4U.com and changed 4096 cycles to 4000 for MADDR[7]. (Note: MADDR was incorrectly labeled as MDATA in previous data sheet.) March 29, 2004: Added Standby mode to Table 16, Power Consumption. April 19, 2004: Added the I2C f.
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